Paul Jarmola

Angestellt, Software Project Manager, Continental Teves AG & Co. oHG, Frankfurt am Main

Frankfurt am Main, Deutschland

Fähigkeiten und Kenntnisse

Project Management
Technical Team Lead
FPGA
Embedded
FAE - Technical Sales
Team Management
Xilinx
Lattice
C++
Microcontroller
Altera
Patent Registration
RTL Simulation
Pilot's Licence
Softwareentwicklung

Werdegang

Berufserfahrung von Paul Jarmola

  • Bis heute 4 Jahre und 6 Monate, seit Jan. 2020

    Software Project Manager

    Continental Teves AG & Co. oHG, Frankfurt am Main

  • 1 Jahr und 2 Monate, Nov. 2018 - Dez. 2019

    Software Projektmanager

    WEBER GmbH - Technik pur
  • 7 Monate, Apr. 2018 - Okt. 2018

    Director Product Development PikeOS

    SYSGO AG

  • 1 Jahr und 5 Monate, Apr. 2016 - Aug. 2017

    Technical Lead Embedded Systems

    Panasonic Automotive & Industrial Systems Europe GmbH

    Project Management Deep Level of Algo/HW/SW/Embedded Understanding Needed Communication Oriented Created Work Packages for External Companies/Contractors Contact to chip companies Involved in Job Interview Process Task at Hand: Automotive Process Orientation Port PC C/C++ Algorithm Code to Embedded Platforms Parallel Image Processing of Optical Flow Algorithms on both ARM and FPGA

  • 3 Jahre und 1 Monat, März 2013 - März 2016

    SFAE - Altera FPGAs

    Arrow Central Europe GmbH

    As a dedicated FAE (dFAE) for Altera FPGA/CPLD products, I am responsible for maintaining customers interest, projects as well as future development plans all enclosed within the scope of the logistics business at Arrow Electronics.

  • 3 Jahre und 7 Monate, Juli 2009 - Jan. 2013

    FPGA Hardware Development Engineer

    Magna Electronics Europe GmbH & Co

    Design FPGAs consisting of: -AXI Interfaces -SPI BUS -I2C BUS -BT656 Video Format -DDR3 Controllers -LVDS CameraLink -UART -Colour Space Conversion -Algorithm Design Creation and maintenance of simulation testbenches Commissioning of hardware interfaces Verification of PCB designs Development tool experience in: -ModelSim -ISE (Xilinx) -EDK -ispLever (Lattice)

  • 1 Jahr und 10 Monate, Okt. 2006 - Juli 2008

    FPGA Hardware Design Engineer

    Ulm University

    -hired externally by Daimler AG to develop a bird's-eye-view system using FPGAs -successfully developed multi-camera processing algorithms using VHDL -realized park assistance algorithms for FPGA -supervised students contributing towards the project

Ausbildung von Paul Jarmola

  • 2 Jahre und 4 Monate, Apr. 2004 - Juli 2006

    Communications Technology (Electrical Engineering)

    Ulm University

    Microelectronics, VHDL/FPGA Embedded Hardware Design

  • 5 Jahre und 8 Monate, Sep. 1998 - Apr. 2004

    Computer Science

    University of Western Ontario

  • 5 Jahre und 8 Monate, Sep. 1998 - Apr. 2004

    Electrical Engineering

    University of Western Ontario

    Electrical Engineering

Sprachen

  • Englisch

    Muttersprache

  • Deutsch

    Fließend

  • Polnisch

    Fließend

  • Französisch

    Gut

  • Ukrainian First Language

    -

Interessen

Trecking
Biking
Flying

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