Dr. Markus Jäger
Selbstständig, FPGA SoC Developer, System Architect Embedded Systems, SciCaTec - Dr. Markus Jäger
Stuttgart, Deutschland
Über mich
Specialist for Signal, Video & Image Processing, Computer Vision and Embedded System Architecture based on FPGAs, SoCs & GPU
Werdegang
Berufserfahrung von Markus Jäger
Bis heute 5 Jahre und 5 Monate, seit 2019
FPGA SoC Developer, System Architect Embedded Systems
SciCaTec - Dr. Markus Jäger
As an enthusiastic FPGA developer, system architect, technical team leader and software developer I support you in your projects in industry and science worldwide. Together with you I would like to overcome the last troubles of your project. In this way we achieve a prosperous collaboration.
7 Jahre und 2 Monate, Okt. 2012 - Nov. 2019
System Architect digital Hardware, FPGA SoC Developer
Carl Zeiss Microscopy GmbHAs System Architect digital Hardware for digital Microscopes, I was responsible for architecture concept and development of FPGA and embedded designs for Signal and Image Processing in the fully digital microscope "Smartzoom 5". In parallel, I held the position of sub-project management of electronics to lead an internal team of developers and coordinated external development partners in international projects. I contributed in the development of the Laser Scanning Microscopes "LSM 880" and "LSM 980".
7 Jahre, Apr. 2011 - März 2018
Doctoral Candidate Computer Engineering (Doktorand Technische Informatik)
Universität Leipzig(extra occupational dissertation to my full-time job in industry; berufsbegleitende Dissertation) As doctoral candidate I developed new digitale SuperSampleRate IIR FIR Filter designs in FPGAs to achieve improved time and energy resolution for pulse processing. Furthermore, I developed two scientific measuring instruments in nuclear electronics. A digital TDPAC spectrometer and a digital data acquisition system for ion beam analysis. https://nbn-resolving.org/urn:nbn:de:bsz:15-qucosa2-210420
In sector of 3D Laserscanning (Lidar) I developed and tested High Speed FPGA Designs and System Architectures for signal and data processing. Additionally I developed hardware close software executed by microcontrollers. I contributed in the development of the 3D Laser Scanning devices "Trimble CX" and "Trimble TX8".
At faculty of physics and earth sciences I developed an experiment for resonance condition control of an interferometer using a Gentoo-Linux real-time regulator.
1 Jahr und 3 Monate, Juli 2005 - Sep. 2006
co-op program (Studentisches Berufspraktikum)
Universität LeipzigAt Institute of Computer Science I developed a hardware configuration manager for partial dynamic reconfiguration in FPGAs.
Ausbildung von Markus Jäger
7 Jahre, Apr. 2011 - März 2018
Doctorate Computer Engineering (extra occupational)
University of Leipzig
(extra occupational dissertation to my full-time job in industry; berufsbegleitende Dissertation) As doctoral candidate I developed new digitale SuperSampleRate IIR FIR Filter designs in FPGAs to achieve improved time and energy resolution for pulse processing. Furthermore, I developed two scientific measuring instruments in nuclear electronics. https://nbn-resolving.org/urn:nbn:de:bsz:15-qucosa2-210420
3 Jahre und 7 Monate, Okt. 2004 - Apr. 2008
Physics (Physik)
University of Leipzig
Bachelor thesis: Extension of a Gentoo Linux with RTAI, LabVIEW and Comedi as digital real-time regulator (Bachelor-Thema: Erweitern eines Gentoo-Linux mit RTAI, LabVIEW und Comedi als digitaler Echtzeit-Regler) Thesis Link: https://nbn-resolving.org/urn:nbn:de:bsz:15-qucosa2-171569
5 Jahre und 8 Monate, Okt. 2002 - Mai 2008
Computer Engineering (Technische Informatik)
University of Leipzig
Diplom thesis: Evaluation of a complete System-on-Chip based on AMBA 2.0 components and the LEON3 (SPARC) processor in Xilinx EDK Thesis Link: https://nbn-resolving.org/urn:nbn:de:bsz:15-qucosa2-166290
Sprachen
Deutsch
Muttersprache
Englisch
Fließend