Yee Yang Tan

Topic: Prototyping and Optimizing a Scaled-out NoC-interconnected Neuromorphic BNN Accelerator • Designed high-speed hybrid emulation framework for verification system and achieved 1 magnitude speedup. • Fixed the target NoC IP from critical system issue at RTL level. • Verified and simulated the framework blocks with VHDL test benches on GHDL, Vivado. • Implemented embedded software for the NoC verification system and PetaLinux SG DMA API with OOP in C.

• Implemented and validated the abstract TLM-based Model for the NoC Interconnects simulator. • Maintained open-source network simulator Ratatoskr, such as design and develop the Ratatoskr NoC simulator's toolkit API design with Python and Jupyter. • Enhanced the Ratatoskr simulator with C++ and SystemC by implementing network topologies (ring, torus), optimizing of PARSEC-benchmark module, developing routing algorithm (torus), etc.

Transformation of Compiled Object between Operating System on the same Architecture. • Designed the software architecture for the program of compiled objects conversion with OOP in C++. • Applied the knowledge of ELF ABI for z/OS IBM Operating System.

• Developed a new, generic design and implemented the program with C++ and git after the analysis of POC. • Validated the functionality and stability of the new toolkit with different test series. • Applied the technique of compiler, linker, and loader including the BIN data structures on OS's Linux on System Z, z/VM, and z/OS.

• Designed the algorithm for the classification of semi-structured data through algorithms that are temporarily optimized. • Programmed the software of image classification based on image hash and locating them in existing files. • Documented the work of previous colleagues and visualize the project blueprint.

• Assisted the students during the tutorial class (Object-oriented Programming C++) with a group of 5 persons.