Usama Minhaj

• Worked as Machine learning engineer for time series sales forecasting of the largest retail store in the world. • Developed preprocessing, feature engineering, hyper optimization, and model selection pipelines using pyspark and SQL. • Performed unit testing to test the functionality of the pipeline. • Worked on object tracking models for embedded AI applications.

• Research on Internet of Things (IoT) and potential 6G wireless technologies under the supervision of Dr. Syed Ali Hassan. • Developed mathematical models and algorithms for finding optimal transmission parameters in the LoRaWAN IoT network. • Optimization techniques included successive interference cancellation (SIC) and machine learning (ML). • Setup IoT networks using Dragino gateways and nodes.

• Worked on FPGAs and RISC-V processor under the supervision of Dr. Rehan Ahmed. • Completed Intel Altera labs using Verilog HDL on Cyclone II as part of the training. • Implemented complete balanced 5 stage pipelined RISC-V ISA on Cyclone II FPGA. Data Hazards were removed using data forwarding, while control hazards were removed using stalling. • Designed 4-way set-associative cache with LRU as replacement policy using SystemVerilog.

Grade: 3.91/4 (German Equivalent: 1.1)