Thomas Hebein

Top-level and IP-level design of analog frontends for telecommunication ICs down to 16nm technologies. Modelling of analog blocks with system verilog; functional simulation of Top-level with xcelium. C-based description of implemented full custom serial interface for programming of control bits of blocks with spectool. Writing of c-based low-level API functions for firmware. API functions use content of spectool. Handling with perforce data management and release management.

Top-level design of analog frontends for telecommunication ICs down to 16nm technologies. Modelling of analog blocks with verilog; functional simulation of Top-level with ncsim. Description of implemented full custom serial interface for programming of control bits of blocks with c-based spectool. Writing of c-based low-level API functions for firmware. API functions use content of spectool.

I started at Lantiq with analog Design of analog filters for frontends of telecommunication-ICs in 65nm technology. Later on I did also vhdl-modelling of analog blocks and functional simulation of whole analog frontend (including small digital parts) with ncsim. My responsibility over the years was on Top-level design, modelling of analog blocks (vhdl, verilog-ams, ...) and functional simulation with ncsim.

Working on a cyclic pipeline-ADCs. Also one project about TRNG (true random number generator).

Working on analog frontends for consumer electronics ICs. Parallel to my work I did a two-year Master study. The master thesis I did also at micronas aboud data interface HDMI.

Diploma thesis about 1.5bit/stage pipelined ADC. A Matlab model for a 10bit pipestage ADC was done, and based on the matlab model the ADC was implemented in schematics, layout and silicon.