Sooraj Sati

writes the final thesis.

Bis 2021, ASIC Design and Verification Engineer, Tech Mahindra Cerium Systems Bangalore

Cerium systems -Tech mahindra, Indien

Über mich

4.8+ years of experience in Design Verification using System Verilog and OVM/UVM • Have good knowledge of AMBA protocols (APB), Basics of PCI-e and SPI Protocol. • Proficient in System Verilog and Verilog hardware language. • Good hands on practice in UVM-SV, and debugging skills. • Have good knowledge in developing Test Benches and Test Plan creation.

Fähigkeiten und Kenntnisse

Verilog
system verilog
uvm
ovm
Perl Scripting
VHDL

Werdegang

Berufserfahrung von Sooraj Sati

  • 4 Jahre und 9 Monate, Jan. 2017 - Sep. 2021

    ASIC Design and Verification Engineer

    Tech Mahindra Cerium Systems Bangalore

    Design and verification engineer

Ausbildung von Sooraj Sati

  • Bis heute 2 Jahre und 10 Monate, seit Sep. 2021

    INFORMATION and Electrical Engineering

    Hochschule Wismar - University of Applied Sciences: Technology, Business and Design

    Masters in Information and Electrical Engineering

  • 4 Jahre, Juli 2012 - Juni 2016

    Electronics and Communication Engineering

    Uttarakhand Technical University

21 Mio. XING Mitglieder, von A bis Z