Ofir Shefer Shalev

Angestellt, Senior FPGA Engineer, DESY

Hamburg, Deutschland

Fähigkeiten und Kenntnisse

FPGA
VHDL
Verilog
Xilinx
Altera
FPGA Prototyping
Logic Design
RTL Design
ASIC
SoC
Debugging
ModelSim
Synopsys EDA
Python
TCL
Linux
Git
SVN
Embedded Systems
Embedded Software
Embedded Linux
Embedded C
Assembly
Device Driver
RTOS
uCOS
Reverse Engineering
ARM
Matlab
Firmwa
R&D
Field Programmable Gate Array (FPGA)
Zynq

Werdegang

Berufserfahrung von Ofir Shefer Shalev

  • Bis heute 8 Jahre und 11 Monate, seit Aug. 2015

    Senior FPGA Engineer

    DESY

    - Developing an innovative system for the control of Particle-Accelerator-Magnets, incorporating 10 dynamic-reconfigurable areas on a single Zynq FPGA. - Performing the complete design, verification and implementation of the new generation of Particle-Detectors using a Zynq7000 FPGA. The Detectors receive data at a rate of over 30Gbps, and send it to the host over 10G Ethernet. - Creating and maintaining the FPGA build-flow-automation scripting environment in Python and TCL

  • 7 Monate, 2015 - Juli 2015

    FPGA Engineer

    Apple

    - Responsible for the prototyping of a high-speed Imaging IP on a Xilinx Virtex-2000 FPGA. - Involved in the prototyping of other IPs using the HAPS-60 and HAPS-70 prototyping platforms.

  • 2012 - 2015

    Senior FPGA Engineer

    Intel Deutschland GmbH

    - Leading the development of Intel® RealSense™ 3D Camera's FPGA prototyping. - Overseeing the meticulous definition and review of design constraints to achieve timing closure on a highspeed multiple asynchronous clock domains design - Successfully registering a reduction in debug count as well as increasing QOR via the integration of the FPGA design into the ASIC's UVM verification environment

  • 2007 - 2012

    FPGA & Embedded SW Engineer

    GOI

    - Presiding over the analysis and routing of SATA communication between multiple storage systems as part of the high speed Xilinx Virtex5 FPGA system design - Overseeing the successful completion of several other projects on Altera FPGA’s - Managing the end to end development of Embedded software - Performing reverse engineering of embedded software

  • 2000 - 2007

    Senior Antenna Engineer

    GOI

    - Supervising a group of 4 antenna engineers as the Head of Antenna Research, designing a host of antennas for innumerable projects - Performing antenna simulations using Zeland IE3D, Microwave Studio CST and TICRA GRASP8 etc. - Gaining extensive experience in the design of RX chains - Overseeing the development and coaching of other team members, devising and implementing new methods and design tools as part of the learning process

  • 1998 - 2000

    Signal Processing Engineer

    Rafael Advanced Defence Systems

    - Developing a Matlab program to read processes and to display RADAR signals, whilst implementing tracking and identification algorithms - Identifying and eliminating various critical bugs in an existing program

Ausbildung von Ofir Shefer Shalev

  • 1996 - 2000

    Electrical Engineering

    Technion – Israel Institute of Technology

    - Majored in Computers, Communications and DSP. - Attained the Dean's list.

Sprachen

  • Englisch

    Fließend

  • Deutsch

    Gut

  • Hebräisch

    Muttersprache

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