Megha Bhat

Topic: Parallel architecture of high throughput JPEG2000 decoder Obtained Grade: 1.3 • Hardware architecture designed for high throughput decoder JPEG2000 • Implemented JPEG2000 decoder for code-block size 8 in VHDL and verification on FPGA by simulation • Carried out comparison of performance of the designed JPEG2000 decoder for different code-block sizes • Programming Language: VHDL, Software Suite: Xilinx Vivado 2018.2 • Target FPGA: Kintex-7 Xilinx family

• Handling of effort and defect tracking using IBM Rational ClearQuest. • Preparation and analysis of test reports • Automation of project management files via VBA • Support of sub-project management in day-to-day business

Project: Radio Colour Connect(RCC) for Peugeot Société Anonyme(PSA) in Electronic Car Multimedia-Infotainment Domain •Software developer responsible for development of adapter service layer for Media component(Bluetooth, iPod and USB) •Involved in requirement analysis, design, coding and unit testing and corresponding documentation for customer specific features according to Automotive-SPICE standards •Experience with Software Development Life Cycles •Programming Language: C++, Software IDE: Eclipse CDT

Aggregate GPA: 2.1 • Electronic Circuits, System and Signal Theory, Intelligent Sensors and Actors, Physical Design of Integrated Circuits, Hardware Verification and Quality Assessment, Software Engineering and Real Time systems, Industrial Automation Systems, Embedded Systems Engineering

Aggregate GPA: 85.34% (1.6 in German grading system) Bachelor Thesis: Adaptive Traffic Signal Control • Determination of traffic density at a signal based on the Google maps traffic data and optimize the signal green time using Image processing • Programming Language: Python