Kaustubh Chaudhari

Angestellt, Senior ASIC Design Engineer, Qualcomm Inc.

San Diego, Vereinigte Staaten

Fähigkeiten und Kenntnisse

verilog
ASIC and FPGA Design
Embedded Systems Design
FPGA
ASIC
Digital Design
Hardware Design
Neuroscience
Medical device
Medical technology
C
C++
FPGA Design
Field Programmable Gate Array (FPGA)
Python
VHDL
SystemC
Embedded Systems
Embedded System Development
Embedded microcontroller
Embedded / Real-Time / RTOS
MatLab

Werdegang

Berufserfahrung von Kaustubh Chaudhari

  • Bis heute 2 Jahre und 10 Monate, seit Sep. 2021

    Senior ASIC Design Engineer

    Qualcomm Inc.

    Currently working in the camera lead team handling premium projects.

  • 2 Jahre und 1 Monat, Sep. 2019 - Sep. 2021

    ASIC Design Engineer

    Qualcomm Inc.

    Working in the Camera team at Qualcomm Technologies Inc. San Diego.

  • 1 Jahr und 8 Monate, Jan. 2018 - Aug. 2019

    Research assistant

    Frohlich Lab

    Designed, developed & modified Neuro-tech devices in Frohlich Lab during and after Master's degree. Also wrote a thesis while working at the lab. Worked on closed loop brain stimulation system to achieve custom stimulation waveform output which could be triggered using inputs by processing real time EEG data or a user. Also worked on design & development of long-term EEG monitoring device from start up which can save research grade data to docking station in MATLAB readable format. Full time Feb-Aug 2019

  • 2 Monate, Juli 2018 - Aug. 2018

    FPGA/ASIC Design Intern

    Wyss Center for Bio and Neuroengineering

    Worked on developing a communication controller on IGLOO2 FPGA from microsemi using verilog HDL between INTAN sampling front-end and a wireless transmitter. The work included dealing with initializing and verifying multiple INTAN chips, acquiring sampled data from them at highest possible sampling rate and then storing/compressing the data to embedded SRAM memory in the FPGA and then combining the data and converting it to an encoded packet to output for transmission.

Ausbildung von Kaustubh Chaudhari

  • 1 Jahr und 5 Monate, Aug. 2017 - Dez. 2018

    Electrical and Computer Engineering

    North Carolina State University

    ASIC and FPGA design with Verilog-ECE 564 Micro-architecture-ECE 563 Embedded system architecture-ECE 560 Embedded system optimization-ECE 561 VLSI system design-ECE 546 Neural Interface Engineering-ECE 505 Analog Electronics-ECE 511 Electronic System Level & Physical Design-ECE 720

  • 3 Jahre und 11 Monate, Aug. 2012 - Juni 2016

    Electronics and Communication Engineering

    Shri Ramdeobaba College of Engineering and Management

Sprachen

  • Englisch

    Fließend

  • Hindi

    -

  • Marathi

    -

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