Joo-Yong Sung
Bis 2019, Physical Design Engineer, Intel Deutschland GmbH
München, Deutschland
Werdegang
Berufserfahrung von Joo-Yong Sung
Bis heute 4 Jahre und 7 Monate, seit Dez. 2019
Physical Design Engineer
Apple Deutschland GmbH
4 Jahre und 3 Monate, Juli 2014 - Sep. 2018
Senior Application Consultant
Synopsys Inc.
I'm senior application consultant for IC Compiler/IC Compiler II and support Samsung Electronics. I'm helping my customers when they have some problems in using ICC/ICC II and makes WA if they want. I had succeeded the first ICC II Top implementation and Design Planing flow in Samsung with 28nm/14nm.
8 Jahre und 8 Monate, Dez. 2005 - Juli 2014
Physical Design Engineer
GCT semiconductor
• Physical implementation and verification for mobile TV and Wimax chips. (RF CMOS process) • Physical implementation and verification for LTE-A/Wimax single chips. • From 200K to 5M instances in digital logic. • Hierarchical Design Experiences. • Post STA for VDSM processes.(90/65nm) • Experienced multiple processes - UMC 130nm/110nm/40nm, Samsung 90nm/65nm/28nm. • Develop Tcl/Tk utilities for P&R • More than 25 full chip tape-outs.
4 Jahre und 5 Monate, Aug. 2001 - Dez. 2005
Engineer
ED-Tech
• Responsible from RTL design to Physical implementation. • RTL design and verification for video de-interlacer, OSD(On Screen Display) and I2C. • TOP RTL coding for several chips. • Performed full chip Synthesis/STA • Performed full chip physical implementation and verification
6 Monate, Juli 2000 - Dez. 2000
Praktikant
Infineon Technologies AG, Munich
I had designed PCBs for PLL test boards. I made libraries for designing PCB and designed PCBs. I have got prize money for Special achievement from company.
Ausbildung von Joo-Yong Sung
3 Jahre und 5 Monate, März 1998 - Juli 2001
Electronic Engineering
Sogang University Graduated School
CAD & Computer Systems
4 Jahre, März 1994 - Feb. 1998
Electronic engineering
Sogang University
Sprachen
Englisch
Fließend
Deutsch
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