Imad Azhaf

Project: Failure management for autonomous driving projects - Creation, update and review of SW specification (SWE3) using DOORS - Update detailed design (SWE2) - Feature, Bug fix and Source code improvement implementation using C/C++ - Debug and testing using Trace32 and Python - QAC/QACPP warning analysis and resolution - Review of Test script (SWE4) - Creation of Flux examples for Insert tool validation - Configuration management using GIT

Project: BCM Root cause analysis tasks: - Customer specification analysis of different SW areas using DOORS - Testing and debug raised issues using different SW versions using C/C++, WinIDEA, AEEE & CANOE - Discuss with DEV teams (3rd parties) - Propose solutions for issues using IBM Rational JAZZ Architecture tasks: - Creation of Provided and Used Interfaces diagram - Creation of Static Interaction diagram - Creation of Signal Flow diagrams (DFD)

Projects: Gateway ATLAS3/3R - Supervising DUT team - Development and preparation of the DUT environment (HOST SW and Embedded SW) using C/C++, Python, Davinci Config tool - Development of tests requested by HW team using Python - Extend the use of DUT to Prototype stage (before EOL stage) - Support different plant and prototype teams (Spain and China) - Support Hardware team analyzing defects and issues highlighted by customer (JLR) Tools: Python, C, Trace32, PCB and Schematic, Eclipse, JIRA, SVN

Projects: USM - Monitoring of metrics of BSW area - Customer and Hardware specification analysis using DOORS - Design of Low-Level Design (LLD) specifications - Implementation of specification of different BSW components using C/C++ - configuration and integration of the MCAL component using Davinci Config tool - Testing and debug of components - LLD & Code review - Customer anomaly report analysis and debug using Trace32 & CANOE

As an FPGA designer am responsible of the following tasks: - The respect of the V development cycle and the DO-254 standard - Validation of the required Design - Development of the different module’s architecture and write VHDL code - Simulation of the RTL Design - Static timing analysis (STA) and analysis of synthesis warnings - Delivery’s estimation and planning - Planning of weekly points with the customer - Proposition of action plans for the design activities success

- Mission: Study and Evaluation of inter-core communication mechanisms of new generation of radar based on DSP C6678 - Tools & technologies: DSP TMS320C6678, SYS/BIOS RTOS, C.

- Mission: Modeling and implementation of a platform for automating competitions ACM - Tools & technologies: WAKANDA, JavaScript, JQuery.

- Mission: Developing a web application for Monitoring Apache server. - Tools & technologies: JAVA/J2EE, Servlet, JSP, JFreeChart, SSH protocol, Shell.

Embedded systems & computer science

Mathematics, physics and engineering science