Dmytro Levit

Design of the FPGA-based (Arria 10) data acquisition system for the Belle 2 experiment. Redesign of the receiver part of the trigger timing system to use the clock-data recovery component, which improved stability of the high-speed links and the trigger timing interface. Design of a new event builder algorithm for PCIe40 board using event reassembly in software. The development included deep optimizations to the DMA driver and the read-out software.

Design, implementation, and performance characterization of the FPGA-based timeslice builder using a Virtex-6 FPGA for the triggerless DAQ of the AMBER experiment. The functionality of the timeslice builder was verified in simulation using the UVVM and OsVVM framework and with the custom data generators programmed to generate realistic data occupancy of the subdetectors. Lecture and the practical course "Signal processing with FPGAs for detector development" aimed at the master-level students.

Implementation of the read-out system of the Belle II pixel detector. The system consists of Virtex-6 and Artix-7 boards which work together to control the detector, read data, build subevents from five sensors, and send them to the DAQ of the experiment. Evaluation and optimization of the high-speed serial links (1.5 Gb/s) over 15 m copper cables between the front-end electronics and the read-out system. I built custom adapter boards to test and optimize signal quality with oscilloscope.