Anish Joboy Augustine

RTL Design Engineer with 4 years experience of working with the global leader in electronics/semiconductor industry. Area of work include: Low Power RTL Design Multi-Power/Voltage Domain Design Expertise using UPF Multi-Clock Domain Design ECO flows Expertise in Static Low power design check tools like SpyGlass LP and VCLP RTL/Gate-Level Simulations and Debug Protocols : PCIe, USB3, USB4, Thunderbolt, Display Port, AMBA Expertise : Digital Design, CDC, STA, Verilog, System Verilog, UPF, Low power, IP design, VCLP, SpyGlass LP (SGLP)