Aditya Garg

Silicon validation and Product development Engineer with expertise in Post-Silicon validation of NAND flash and Sever-CPU, having an interest in Data-Science, Machine Learning, and Neural Networks. Expertise includes but is not limited to CPU collateral development and validation. Product feature feasibility study generating targeted test-plan, and performing failure analysis, to drive from silicon validation/bring-up to high volume manufacturing meeting yields goals and Test-time targets. Working expertise also includes python scripting, RTL simulation/emulation runs on SOC validating DFD architecture capturing signal trace and debugging using waveform dump/Verdi. Test hardware expertise include Advantest T5773ES, T5831ES, 93K Other theoretical expertise includes RTL/Gate Simulations, Timing Analysis, DFT Architecture like Scan/ ATPG/ JTAG/TAP, MemoryBIST, LogicBIST.