Abid Anjum
Angestellt, IC Layout Engineer, Intel Deutschland GmbH
Munich, Deutschland
Werdegang
Berufserfahrung von Abid Anjum
Working on RFIC Physical Layout and Transistor Level Extraction
-Developing an EDA tool to wrap around Synopsis IC Compiler for Branchless Maze Routing of on-chip Special Interconnects in SoC Layout. -Worked on Cadence Logic Simulator extension to extract gate-level switching of IPs that is used to analyze RTL design's vulnerability for pre-silicon functional verification.
Ausbildung von Abid Anjum
2 Jahre, Okt. 2013 - Sep. 2015
Elektrotechnik
Technische Universität München
Electronics Engineering
4 Jahre und 1 Monat, Sep. 2003 - Sep. 2007
Electrical Engineering
University of Engineering and Technology, Taxila
Computer Engineering
Sprachen
Englisch
Fließend
Deutsch
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